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Description: 该Verilog程序提供了一种控制IDT系列Ram的读写操作程序,每次读写750个16位的数。-The Verilog program control IDT provides a series of read and write operating procedures Ram, 750 each to read and write the number 16.
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Size: 1024 |
Author: 刘进 |
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Description: FPGA和双端口RAM的DDS任意波形发生器的实现-FPGA and dual-port RAM of the DDS Arbitrary Waveform Generator
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Size: 513024 |
Author: 刘磊 |
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Description: 直接频率合成DDS模块的ise工程,可以直接下载,在Spartan3/Spartan3E上验证通过。该DDS模块可以产生双通道的不同频率的正弦波,也可以产生同频的任意相位差的相移波形。本模块累加器位数为32位,可以产生12位相位精度12位量化精度的正弦波。该设计例化一个Block Ram,为节省储存空间仅需要储存1/4周期的数据。根据需要,可以重新修改数据,改变波形。-DDS direct frequency synthesizer module ,ise project, can be directly downloaded through the Spartan3/Spartan3E and tested successfully. The DDS module can generate two-channel sine wave of different frequency, or produce the same frequency arbitrary waveform phase difference of the phase shift. There is a 32-bit accumulator to generate 12 bit phase-precision 12-bit quantization precision of the sine wave. Cases the design of a Block Ram, in order to save storage space need to store only 1/4 cycle of data. Necessary, can modify data, change the waveform.
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Size: 471040 |
Author: 郭先生 |
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Description: verilog语言编写的一个接口文件,使用乒乓ram-verilog language of an interface file, use the ping-pong ram
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Size: 1024 |
Author: yaop |
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Description: Verilog编写的代码,单口RAM用程序控制地址,而不是在仿真文件里面控制地址-Verilog code is written, single-port RAM with the process control address, rather than inside the control address of the simulation file
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Size: 1438720 |
Author: niuniu |
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Description: 用ram存储顺序,用此方法也可以实现其他的顺序数据,代码用verilog编写-Ram memory with the order can be achieved using this method also the order of the other data, write code using verilog
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Size: 2048 |
Author: zhm |
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Description: 快速冒泡排序基于FPGA实现,有测试文件以及设计图,实现1024*32位数序的多数排序,突破传统是的REG类型少数排序,利用RAM,针对RAM中的无序数的地址调换,达到排序目的,仅供学习交流-Rapid bubble sort based on FPGA, there are test documents and design drawings to achieve 1024* 32-digit sequence of the majority of sorting, breaking tradition is a REG types of minority sorting, the use of RAM, the disorder for the RAM address of the number of exchange, to sort purpose, only to learn the exchange of.
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Size: 5120 |
Author: 柳泽明 |
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Description: verilog 实现的一个双口RAM及其控制模块.我通过先存入64个数据在读出仿真通过。-verilog implementation of a dual-port RAM.
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Size: 1024 |
Author: 世海 |
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Description: 压缩包中包含了用Verilog编写的视频控制模块,实现PAL制式到VGA制式的实时转换,同时包含了VGA专用ram配置模块,可直接实用-Compressed package includes the preparation of the video with the Verilog control module, PAL format to achieve real-time conversion to standard VGA, VGA also includes dedicated ram configuration module can be directly useful
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Size: 79872 |
Author: 熊文 |
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Description: 用blockram实现移位寄存器,开发语言为verilog hdl-Shift register with blockram achieve the development language for the verilog hdl
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Size: 148480 |
Author: 郭淮 |
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Description: Spartan-3 系列 FPGA 中的 Block RAM 的使用-using the block RAM in Spartan-3 FPGA
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Size: 32768 |
Author: lishiwei |
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Description: actel fusion startkit FPGA开发板试验例程,可实现2k8的双口ram,实现数据存储,缓冲。包含verilog HDL 语言源码-actel fusion startkit FPGA development board test routines, can be realized 2k8' s dual-port ram, achieving data storage, buffer. Language source code contains the verilog HDL
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Size: 608256 |
Author: zhangyujun |
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Description: verilog 块ram写入操作 fpga xilinx ip core-Verilog block_ram module fpga xilinx ip core
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Size: 2048 |
Author: y_gt |
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Description: CPU Local RAM Verilog Module
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Size: 28672 |
Author: jc |
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Description: Verilog Synthesisable RAM source code
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Size: 214016 |
Author: jc |
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Description:
This file with the wavelet transf
Mallat implementation of wavelet
Verilog hdl code modules for radi
Modelsim 6.6 crack, can be used f
A written using Verilog DDR2 cont
Simple CPU VHDL implementation an
Dual-port RAM design, using Veril
Verilog language, a hardware-base
FPGA embedded project combat, Man
Application FPGA, FPGA-chip hardw
Mallat implementation of wavelet
Layer of one-dimensional wavelet
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Size: 1852416 |
Author: sansfroid |
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Description: 同步静态RAM读写程序,可用作模块,已通过ISE12.4验证-Synchronous Static RAM read and write procedures, can be used as modules, have been verified by ISE12.4
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Size: 1024 |
Author: koo |
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Description: 该源码包是2.0版本的AMBA总线的Verilog语言模型,主要包括5个部分:AHB总线仲裁器,AHB-APB总线桥接器,AHB总线上从设备ROM模型,AHB总线上从设备RAM模型,参数定义。-This source code package is the model of V2.0 AMBA bus of ARM company, It mainly includes the following five parts: the AHB arbiter,AHB-APB bridge, AHB_Rom_Slave, AHB_Ram_Slave,Defines.
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Size: 17408 |
Author: jinjin |
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Description: 利用verilog实现的双口RAM。文件包含工程文件,仿真文件,使用方便。-Using verilog implementation of dual-port RAM. File contains the project files, simulation files, easy to use.
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Size: 219136 |
Author: sue |
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Description: 双端口ram的verilog程序,经过验证,可编译可用,-dual pot ram
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Size: 1024 |
Author: lee |
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